| Maximum | Measured | Memory | ||
|---|---|---|---|---|
| Processor | Computer | Efficiency | Efficiency | Bandwidth |
| Bound [%] | [%] | Use [%] | ||
| Nvidia Tesla-100 | Summit | 2.69 | 1.5 | 56 |
| Intel Xeon Phi "KNL" | Cori | 4.67 | 1.5 | 32 |
| Fujitsu SPARC VIIIfx | K | 11.71 | 5.3 | 45 |
| Fujitsu SX/ACE | SX/ACE | 23.44 | 11.4 | 49 |
The theoretical memory bound to the HPCG efficiency (the 3rd column - see the previous page) is about twice as much as the true measured HPCG efficiency (the ratio of the HPCG performance (Top500, the column "O") and the peak performance (Top500, the column "R")) for any of 4 computers in the table. This means that the limited memory bandwidth is still used to about 50% only.
One of the LOWAIN goals is to make a better use of the memory bandwidth using the ORPA memory controller (see later), so that the true HPCG efficiency of a computer (the 4th column) is as close to the memory-bandwidth upper bound (the 3rd column) as possible.